Examining Current Commodity CMPs for Fault Isolation

chip level. In turn, this enables cost benefits from reduced component count. Additionally, enhanced resource sharing leads to better performance. On-chip components can now be easily shared to improve resource utilization, such as core sharing via hyperthreading, shared caches, and I/O interfaces. However, the same features of multicore processors that offer benefits can also present drawbacks. In particular, the increased levels of consolidation and integration lead to important isolation concerns—for performance, security, and fault tolerance. Fault tolerance is an area of major concern. This is a particularly important issue given that recent studies have shown dramatic increases in the number of hardware errors when scaling technology to smaller feature sizes.4 Developers have encountered two main kinds of errors. First, defects in the silicon cause permanent or intermittent hardware faults, resulting in wear out over time and leading to hard errors. Second, electrical noise or external radiation can cause transient faults when, for example, alpha radiation from impurities or gamma radiation from outside changes random bits, leading to soft errors. With CMPs, the fault-tolerance problem is compounded because a fault in any single component can lead to the failure of the entire chip. The failure in time (FIT) of cores, caches, memory, or I/O components combines to provide a high FIT for the CMP. Future CMP Resource sharing in modern chip multiprocessors (multicores) provides many cost and